1. Field of the Invention
The present invention relates to a technique of estimating simultaneous switching noise generated by simultaneously operating input/output signals of a plurality of pins in a semiconductor device, and more specifically to a technique of acquiring the basic characteristics of the noise.
2. Description of the Prior Art
Conventionally, the power supply oscillation between the ground of a device package or the pin of a power supply, and the ground of an intra-device die or the reference level of a power supply is referred to a ground bounce or a power supply sag, and is one of main factors of erroneous switching.
Recently, an FPGA (field programmable gate array) attracts attention as a semiconductor device in which the pin arrangement, circuit configuration, etc. can be arbitrarily set by a user. With an increasing number of I/O pins of the FPGA and a higher speed of an interface signal, a number output pins simultaneously operating cause an outstanding ground bounce or power supply sag. Therefore, these events are generally referred to as simultaneous operation signal noise (SSN (simultaneous switching noise) or SSO noise (simultaneous switch output noise)).
The amount of SSO noise depends on the pin arrangement of the FPGA. Therefore, in the designing step of a PCB (printed circuit board) loaded with the FPGA, it is necessary to estimate the amount of SSO noise generated on the basis of the pin arrangement of the FPGA to appropriate operating an FPGA device.
As a conventional technology of performing a simulation of SSO noise, general-purpose circuit analytic simulator software etc. referred to as a SPICE (simulation program with integrated circuit emphasis) developed by an integrated circuit group of the Electronics Research Laboratory and the Department of Electrical Engineering Computer Science (EECS) of University of California, Barkley is well known.
In addition the following patent documents 1, 2, etc. are also known as related art.
However, a simulator such as a SPICE can perform a relatively correct simulation of the SSO noise, but has the problem that the simulation takes an enormously long time.    [Patent Document 1] Japanese Published Patent Application No. H10-127089    [Patent Document 2] Japanese Published Patent Application No. 2004-205095